(a) Field of the Invention
The present invention relates to a scanning driver of a display device. More specifically, the present invention relates to a gate driver of a poly-silicon thin film transistor liquid crystal display (TFT-LCD) having a number of pixels.
(b) Description of the Related Art
In a TFT-LCD, an electric field is supplied to a liquid crystal layer having an anisotropic permittivity that is injected in between two panels, and the amount of light that permeates the panels is adjusted by controlling the strength of the electric field, and thereby obtaining desired pixel signals.
A TFT-LCD has a predetermined number of pixels depending on desired resolutions. Resolutions are categorized as an extended Graphics Array (XGA) with 1024xc3x97768 pixels, a Super Video Graphics Array (SVGA) with 800xc3x97600 pixels, and a Video Graphics Array (VGA) with 640xc3x97480 pixels. Hence, each TFT-LCD with a different resolution has a different driving frequency that drives a predetermined number of pixels.
When a TFT-LCD shows images of different signal formats using a fixed number of pixels, it is referred to as a multisync function.
For office automation (OA) products, the XGA device additionally supports SVGA or VGA formats to provide such a multisync function. For audio and video (ANV) products, video signal formats are categorized into the National Television System Committee (NTSC) format and the Phase Alternating by Line system (PAL) format, and display modes are categorized into a full mode, a wide mode, a normal mode, and a cinema mode.
However, unlike amorphous silicon LCDs, when implementing the multisync function in poly-silicon TFT-LCDs that integrates a drive circuit, the circuit becomes complex, decreasing the yield of the LCD panels and increasing the panel size.
It is an object of the present invention to implement the multisync function using a simple circuit configuration and improve the yield of liquid crystal display (LCD) device panels.
In one aspect of the present invention, an LCD device comprises an LCD panel including a plurality of gate lines, a plurality of insulated data lines crossed with the gate lines, and a plurality of thin-film transistors (TFTs) each including a gate electrode connected to a gate line, and a source electrode connected to a data line; a data driver supplying per line a gray image voltage through the data lines; a gate driver including a plurality of first blocks each receiving a first and second clock signal, and a plurality of second blocks each receiving a third and fourth clock signal, the first and second blocks each including a predetermined number of latch blocks connected in series, and in a multisync mode, concurrently outputting a plurality of gate driving signals to a plurality of gate lines for a period determined by the predetermined number of the latch blocks; and a timing controller outputting a first clock signal, a second clock signal that is an inverted first clock signal, a third clock signal, and a fourth clock signal that is an inverted third clock signal, and changing the status of the first through fourth clock signals according to normal or multisync modes.
The gate driver comprises a shift register unit in which first and second blocks are alternately connected in series; and a logical arithmetic unit including a plurality of logical arithmetic blocks that receives outputs of an (n)th latch block and an (n+1)th latch block and performs a logical arithmetic operation, with each output terminal of the logical arithmetic block including a logical arithmetic means connected to a corresponding gate line.
The first or second block is characterized in that at least in the multisync mode the outputs of the latch blocks positioned in the first and second places are identical with the output of the last latch block of a previous block.
The shift register unit is characterized in that the first and last blocks each include two latch blocks and other blocks include four latch blocks.
The latch block, a shift register, comprises a first three-phase inverter operative according to the first or third clock signals; an inverter having an input terminal connected to an output terminal of the first three-phase inverter; and a second three-phase inverter having an input terminal connected to an output terminal of the inverter, and having an output terminal connected to the input terminal of the inverter, and operating according to the second or fourth clock signals.
The logical arithmetic block is an AND gate.
The logical arithmetic block comprises an AND gate performing a logical AND operation on outputs of the (n)th and (n+1)th latch blocks; a first inverter inverting an output of the logical AND gate; and a second inverter inverting an output of the first inverter.
The timing controller is characterized in that the first and third clock signals are identical and the second and fourth clock signals are identical in the normal mode, and the first and fourth clock signals are identical and the second and third clock signals are identical in the multisync mode.